Cannot be Enabled FrontPanel when okWireOut and okPipeOut are implemented


Now, I’m facing some strange thing…
I want to design as blow (1-okPipeIn, 1-okPipeOut, 2-okWireOut),

wire [17*4-1:0]  ok2x;
okHost okHI(
	.hi_in(hi_in), .hi_out(hi_out), .hi_inout(hi_inout), .ti_clk(ti_clk),
	.ok1(ok1), .ok2(ok2));

okWireOR # (.N(4)) wireOR (ok2, ok2x);

okPipeIn   pipeIn0 (
	.ok1(ok1), .ok2(ok2x 0*17 +: 17 ]), .ep_addr(8'h80), 
	.ep_write(pipeIn_writeReq), .ep_dataout(pipeIn_dout)

okPipeOut  pipeOut0 (
	.ok1(ok1),.ok2(ok2x 1*17 +: 17 ]), .ep_addr(8'ha2), 
	.ep_read(pipeOut_readReq),  .ep_datain(pipeOut_din)

okWireOut  epWire_systemStatus (
	.ok1(ok1), .ok2(ok2x 2*17 +: 17 ]), .ep_addr(8'h20), 

okWireOut  epWire_oData_register (
	.ok1(ok1), .ok2(ok2x 3*17 +: 17 ]), .ep_addr(8'h21), 

This case,

// Download the configuration file.
if (okCFrontPanel::NoError != dev->ConfigureFPGA(CONFIGURATION_FILE)) {
	printf("FPGA configuration failed.\n");
	delete dev;

could be NoError, but

if (false == dev->IsFrontPanelEnabled()) {
	printf("FrontPanel support is not enabled.\n");
	delete dev;

became false, so could not be enabled…

I have analysis it long time, finally,
if ok1 of okPipeOut is changed to the other signal (disconnect it from ok1-bus,
don’t care function, just focus on enabled or not),
became true, could be enabled,

if ok1 of okWireOut is changed to the other signal,
also became enabled.

So, it seems conflict between ok1 of okPipeOut and ok1 of okWireOut,
but both ports is just INPUT in okLibrary.v, or simumation model.
Onlu okHost drives ok1.

I could not find any mistaking in my HDL (Of course, Syns/APR is OK, on simulation, work well my HDL).

May I ask you to give me any suggestion to solve my trouble??


PS. my environment is as follows,
Front-panel : 4.0.6,
API : C++ with Visual C++ 2008,
PC : Win-XP,

Thanks again