Can one determine the PIPEIN word count on the FPGA side with VHDL/Verilog?

IT would be nice to know how many words a PIPE transfer is requesting. Is this possible using any VHDL construct? Currently, I have to count the words using the write enable/read enable lines.


This is not done automatically with the “atomic” action of a pipe transfer. However, you could send this information ahead of time using a WireIn (or multiple WireIns).