BufferedPipes In and Out


Hi Jake,

do you have any waveform diagrams of showing how long and when the data is available when the signals(read/write) are changed to the bufferedPipe components. Also it would be very helpful if you have any sample vhdl code that uses these components, as i am having some problems getting them to work.



Hi Nick-

The PipeTest sample that is included with the latest release includes a very simple instantiation of the BufferedPipe.

The BufferedPipe is actually constructed from a standard PipeIn (or PipeOut) module and a slightly modified asynchronous FIFO from Xilinx’s XAPP131 application note. There are timing diagrams in that note. The only difference between our construction and XAPP131 is that our buffer is suited to the size of the Spartan-3 block RAM (16384 bits).

If you wanted to build a more custom version of the BufferedPipe, you could easily do so by instantiating a CORE FIFO from the Xilinx CORE generator and connecting it to the PipeIn / PipeOut module. The PipeIn/PipeOut modules were designed to work seamlessly with the FIFOs from Xilinx.

Of course, to use a CORE module, you need at least Xilinx ISE BaseX. The free WebPack software will not allow you to build or use cores.