Buffered PIPE


#1

I am trying to implement a design using a buffered pipe in, a buffered pipe out and a wire in. The wire in is an enable signal that connects the input to the output. My C file does not work. The file is:
#include
#include
#include
#include
unsigned char buf1[2];
unsigned char buf2[2];
using namespace std;

int main ()
{
// Create an instance of the okCUsbXEM3001v2.
okCUsbXEM3001v2 *xem = new okCUsbXEM3001v2();

// Open the first available device.
xem -> OpenBySerial();
// Configure the PLL using the stored EEPROM settings.
okCPLL22150 pll;
//This method retrieves the current PLL configuration from the on-board XEM EEPROM.
//The pll object is then initialized with this configuration.
xem -> GetEepromPLLConfiguration(pll);
//Configures the on-board PLL via the I2C bus using the configuration information in
//the pll object
xem -> SetPLLConfiguration(pll);
// Download a configuration file to the FPGA.
xem -> ConfigureFPGA(“top_module.bit”);

xem->SetWireInValue(0x03,0xff);
xem->UpdateWireIns();

buf1[0]=‘8’;
buf1[1]=‘2’;

cout <<< WriteToPipeIn(0x9c, 2, buf1);
//Read 2 bytes from PipeOut 0xA0.
xem -> ReadFromPipeOut(0xa3, 2, buf2);
cout <<<buf2;
}


#2

When you say that your C file does not work, do you mean that it does not compile? Or does it crash? Or does it just not perform the desired functionality?

What does your FPGA logic involve?


#3

It does compile and it does not crash but there is no output from the board.


#4

Is there help available


#5

chameleon-

Have you been able to confirm that the words are being written to the FPGA correctly? That is, is the WriteToPipeIn being executed properly on all sides?

Or is it the ReadFromPipeOut that is not working? Are the signals being delivered out of the PipeOut endpoint to your logic?

Have you tested the samples involving pipes? PipeTest, for example, includes some logic to test Buffered Pipes. DESTester includes logic to send and receive blocks of data with processing in-between. Have you modeled your code on one of these samples?

What have you done already to debug this? What does your FPGA logic look like? Is the FPGA being configured properly? Can you confirm this by checking “IsFrontPanelEnabled” to verify that the firmware recognizes your FPGA design?