Im using a buffered pipe in but for some reason the first byte I read from the pipe always seems to be zero. I assert the read line and nothing seems to come out. I have checked that the pipe is not empty. Currently all I am doing is filling the pipe from the PC with 1 to 9, yet what I get out 0 to 8. The timing all looks ok its just that when read is asserted nothing but zero comes out on the next clock cycle.
Im using the DLL.
Anyone got any ideas ?
Can you tell me what versions you’re running?
FrontPanel version?
XEM Firmware version?
Front Panel Version 1.3.1
XEM firmware version 1.2
Using VC6 and the DLL.
Hi…
You may want to upgrade your firmware (and probably HDL modules) to the latest revs that are included with 1.3.1. XEM3001v1 firmware is currently at version 1.6.
The topic below may be a good read:
http://forums.opalkelly.com/showthread.php?t=71
A while back we posted a problem (and fix) for the buffered pipe out and general pipe timing. However, I do not think this affected pipe ins.
One thing you can do to try to debug…
You can attach another okPipeIn to the host interface. Give it the same endpoint address. This second PipeIn will mirror the one in the BufferedPipeIn to show you when EP_WRITE is being asserted (and to make sure that it is).
Alternatively, BufferedPipeIn is quite simple: a Xilinx FIFO and an okPipeIn – directly connected as you would expect. If you build one yourself (rather than using our pre-built one), you will have access to more signals to help determine where the problem is.
Since Xilinx has included the CORE generator in their recent 8.1i release, the preferred way of building a “buffered pipe” is to use the PipeIn or PipeOut in conjunction with a CORE. The COREs are more configurable than our buffered pipes, provide the same functional connections, flexible sizes (big bonus!!) and result in more efficient use of resources.