BTPipeOut with FIFO


#1

Hello,

I have trouble with block throttled out pipe transfers. For my first steps with the XEM6010-LX45 I’m using a block throttled out pipe to transmit counter values over USB.

I’m writing 16 values into a FIFO. After writing these values the counter is reset. The width of the data in bus is 32 bit. This FIFO is directly connected to a okBTPipeOut component (EP_READ is connected to the FIFOs RD_EN).

Is it correct that I read 164 bytes via ReadFromBlockPipeOut(0xA0, 164, 16*4, buf) for emptying the endpoint?

Anyway, in a loop I’m doing the call: dev->ReadFromBlockPipeOut(0xA0, 164, 164, buf);

When displaying the read data I see the following error:

(…)
PipeOut Transfer no. 5, read_bytes=64=
0 0 0 0
1 1 1 1
2 2 2 2
3 3 3 3
4 4 4 4
5 5 5 5
6 6 6 6
7 7 7 7
8 8 8 8
9 9 9 9
10 10 10 10
11 11 11 11
12 12 12 12
13 13 13 13
14 14 14 14
15 15 15 15

PipeOut Transfer no. 6, read_bytes=64=
0 1 1 1
3 1 3 3
2 3 2 3
3 3 3 3
4 4 4 4
5 5 7 5
6 6 6 6
7 7 7 7
8 8 8 8
9 9 9 9
10 10 10 10
11 11 11 11
12 12 12 12
13 13 13 13
14 14 14 14
15 15 15 15
(…)

After some Transfers, like here in the sixth (first, second and third row), there are errors that actually cannot be explained because of incorrect write operational into the FIFO. The counter is connected to the DIN bus by concatinating 4 8-bit counter values. Timing errors also shouldnt be the problem here.

I guess that in the communication between FIFO and okBTPipeOut itself there should be something inccorect. Do you have any idea?

The FIFO has a read latency of 1.

By the way, I’m using ISE 14.6. The suplied ngc netlists are generated with ISE 13.1. Is there perhaps an incompatibility problem?

My frontpanel version is 4.2.6

Regards,
Jan


#2

Please post the HDL that instantiates the FIFO and connects the FIFO to the BTPipeOut.


#3

— Begin quote from Opal Kelly Support;4186

Please post the HDL that instantiates the FIFO and connects the FIFO to the BTPipeOut.

— End quote

I extended the Counter example with an okBTPipeOut as follows. The reset signal for the VAL_GEN comes from a trigger in. In the VAL_GEN entity I instantiate the FIFO and connect it to the pipe.

epA0: okBTPipeOut
port map
(
	okHE=>okHE,
	okEH=>okEHx( 6*65-1 downto 5*65 ),
	
	ep_addr => x"A0",
	ep_read => EP_READ,
	ep_blockstrobe => EP_BLOCKSTROBE,
	ep_datain => EP_DATAIN,
	ep_ready => EP_READY
);

VAL_GEN_C: VAL_GEN
port map
(
	SYS_CLK => sys_clk,
	RESET => reset2,
	
	EP_DATAIN => EP_DATAIN,
	EP_READY => EP_READY,
	EP_READ => EP_READ,
	EP_BLOCKSTROBE => EP_BLOCKSTROBE
);
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity VAL_GEN is
	port
	(
		SYS_CLK: in std_logic;
		RESET: in std_logic;
		
		EP_DATAIN: out std_logic_vector(31 downto 0);
		EP_READY: out std_logic;	
		EP_READ: in std_logic;
		EP_BLOCKSTROBE: in std_logic
	);
end VAL_GEN;

architecture BEHAVIOR of VAL_GEN is

component MY_PIPE_FIFO IS
  port (
    clk : IN STD_LOGIC;
    rst : IN STD_LOGIC;
    din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    wr_en : IN STD_LOGIC;
    rd_en : IN STD_LOGIC;
    dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
    full : OUT STD_LOGIC;
    almost_full : OUT STD_LOGIC;
    wr_ack : OUT STD_LOGIC;
    overflow : OUT STD_LOGIC;
    empty : OUT STD_LOGIC;
    almost_empty : OUT STD_LOGIC;
    valid : OUT STD_LOGIC;
    underflow : OUT STD_LOGIC;
    data_count : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
  );
end component;

type STATE_TYPE is (IDLE, WAIT_FOR_FIFO_RESET, CHECK_FOR_EMPTY_FIFO, WRITE_INTO_FIFO, WAIT_FOR_EMPTY, READY_STATE);
signal STATE, NEXT_STATE: STATE_TYPE;

signal COUNT_EN: std_logic;
signal COUNTER_RESET: std_logic;
signal COUNT: unsigned(31 downto 0);

signal DATA_COUNT: std_logic_vector(6 downto 0);
signal EMPTY: std_logic;
signal RD_EN: std_logic;
signal WR_EN: std_logic;
signal DIN: std_logic_vector(31 downto 0);

begin


MY_PIPE_FIFO_C: MY_PIPE_FIFO
port map 
(
	clk => SYS_CLK,
	rst => RESET,
	din => DIN,
	wr_en => WR_EN,
	rd_en => EP_READ,
	dout => EP_DATAIN,
	full => open,
	almost_full => open,
	wr_ack => open,
	overflow => open,
	empty => EMPTY,
	almost_empty => open, 
	valid => open,
	underflow => open,
	data_count => DATA_COUNT
);


STATE_REG: process(SYS_CLK, RESET)
begin
	if RESET = '1' then
		STATE  '0');
	elsif SYS_CLK = '0' and SYS_CLK'event then   -- Falling edge !
		DIN <= Std_logic_vector(COUNT(7 downto 0)) & Std_logic_vector(COUNT(7 downto 0)) & Std_logic_vector(COUNT(7 downto 0)) & Std_logic_vector(COUNT(7 downto 0));
	end if;
end process;

end BEHAVIOR;

#4

The problem was that I used the wrong clk for my design and the trigger in, which I use to reset my design. When I use OkClk for both trigger and my user design it runs without errors.