Asynchronous FIFO generate


#1

Hi
Now I’m using the XEM6310 LX-45 board. I want to generate asynchronous FIFO to avoid clock domain crossing problems. I have some questions about the FIFO and pipeout and blockpipeout opearations. I read the manual several times and I understood about the sequences.
In my circumstances, read clock is 100.8MHz(okClk) which comes from the FPGA and write clock is 100MHz which comes from the ADC(external sources , generated by 200MHz crystal oscillator). I received data using BTPipeOut ,

fifo_test DATA_FIFO(.rst(rst),.wr_clk(~clk_100M),.rd_clk(okClk),.din({12’d0, epA3wire}),
.wr_en(~rst),.rd_en(pipe_out_read),.dout(dataout),.full(full),.empty(empty),.prog_empty(prog_empty));
okBTPipeOut epA3(.okHE(okHE), .okEH(okEHx[ 0*65 +: 65 ]), .ep_addr(8’hA3), .ep_read(pipe_out_read), .ep_blockstrobe(), .ep_datain(dataout), .ep_ready(~prog_empty));

FIFO read/write width = 32 , depth = 32768.

  1. If i use BTPipeOut , Is it correct for the read operation to occur when the data fills the FIFO fully?
  2. When the FIFO filled with data, I would like to reduce the FIFO depth by reading and sending it when it is written(FIFO depth maybe 16,32,64 ) . Is it right to use Pipeout in this case? I changed pipeout and fifo to the following, but it did not work. What should I do ?

okPipeOut epA3(.okHE(okHE), .okEH(okEHx[ 0*65 +: 65 ]), .ep_addr(8’hA3), .ep_read(pipe_out_read), .ep_datain(dataout));
fifo_test DATA_FIFO(.rst(rst),.wr_clk(~clk_100M),.rd_clk(okClk),.din({12’d0, epA3wire}),
.wr_en(~rst),.rd_en(pipe_out_read),.dout(dataout),.full(full),.empty(empty),.prog_empty(prog_empty));

  1. In my situation, which FIFO is right for me?
    I use standard FIFO.

Thanks.