Another RAMTest question

Hello All,

I ran across something interesting about the RAMTest application, which I can’t figure it out for the life of me. I am able to write and read to the RAM just fine with the HDL provided. I’ve also managed to get the RAMTest working in labview. I noticed, however, that in the C++ code a reset is issued before both a read and a write. I tired to run this program without a reset between and write and a read and it would not work. I was wondering if anyone had experienced something similar, and whether or not the sdramctl could be modified to allow for this. It seems counter intuitive to have a reset between two actions in a state machine, at least for me anyway.


Absolutely. You’re free to modify the sources as you require.

Could you explain to me why the reset was necessary? I need to know if it needs to be redesigned if it will not work without a reset in between.