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I translated the verilog top module to VHDL for anyone that was having problems or just to save time. The controller is still in verilog. I am using Xilinx Webpack 9.2. I just used the same C++ executable as previous example to test it. It ran fine 100 passes no fails.
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could you explain why your okWireIn instantiation has a ok2 port? All the examples I've seen use something like:
ep00 : okWireIn port map (ok1=>ok1, ep_addr=>x"00", ep_dataout=>ep00wire);