Place and Route warning

Xilinx FPGA
1

I am using an XEM 6010 LX45. When compiling my bit file I get a place and route warning about two signals with no load.

Par:288 - The signal okHI/core0/core0/a0/cb0/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM1_RAMD_O has no load. PAR will not attempt to route this signal.
Par:288 - The signal okHI/core0/core0/a0/cb0/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM2_RAMD_O has no load. PAR will not attempt to route this signal.

I just want to know why this is happening. It seems to be coming from the OK interface stuff that I have no control over. I ignore them and everything works fine. Im just curious if I can somehow get rid of them

2

Unfortunately, Xilinx tools spit out a TON of warnings that are safe to ignore. This is just a no-load net.

The problem is that some of the warnings are important, so it’s hard to get through the Xilinx tool output and drill down to the important things. It comes with experience.