Need some vhdl help

VHDL / Verilog Discussion
1

Hi guys
i wrote this code for a simple counter , 1 to 9. Apparently, it compiles properly including pin assignments but when i go to program, nothing show up on there. Ive tried other vhdl projects and they program fine. any ideas?

thanks!

code---------
Library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY counter IS

PORT (CLOCK : IN STD_LOGIC;
S : OUT STD_LOGIC_VECTOR (6 DOWNTO 0));
End counter;

ARCHITECTURE mylogic OF counter IS

signal count : std_logic_vector (25 DOWNTO 0);
signal a : std_logic;
signal D : std_logic_vector (3 DOWNTO 0);

BEGIN PROCESS (CLOCK)
BEGIN

IF (CLOCK’EVENT AND CLOCK = ‘1’) THEN

count <= not ((not D(1) and D(2)) or D(3) or (D(1) and not D(2)) or (D(2) and not D(0)));

END PROCESS;
END mylogic;

using quartus 2 for a cyclone II board.

2

hey,
you can try this:
Library Ieee;
Use ieee.std_logic_1164.all;
use Ieee.std_logic_arith.all;
use Ieee.std_logic_unsigned.all;

entity count is
port (
clk: in std_logic;–clk
rst: in std_logic;–rst
num_out: out bit_vector (6 downto 0) );

end count;

architecture arc_count of count is
signal cnt:std_logic_vector (3 downto 0);
signal count0: std_logic_vector (3 downto 0);
begin

process(clk,rst)
begin
if rst=‘1’ then cnt num_out num_out num_out num_out num_out num_out num_out num_out num_out num_out null;
end case;
end if;
end process;
end arc_count;