I tried looking up in the datasheet of ZEM4310. I would like to know which FPGA pins are connected to the on-board 50 MHz and 100.8 MHz from the host interface.
From looking at zem4310.qsf, there is this A12 pin which is assigned to sys_clk. Is this 50 MHz or 100.8 MHz?
Should this information be included in the ZEM4310 datasheet/manual?