MicroBlaze

Obviously it is the only method availble.

I wouldn’t call it reasonable since you now have a huge peripheral with 256 individual address.

The worst part is what to do if I need to add something else onto the same port. I can’t, without doing some rather strange kludges.

I guess I had just expected a more finished product, and I hope I gave them a simple enough example to motivate them to fix the problem.

Bill

— Begin quote from sonoranbill;1280

Obviously it is the only method availble.

I wouldn’t call it reasonable since you now have a huge peripheral with 256 individual address.

The worst part is what to do if I need to add something else onto the same port. I can’t, without doing some rather strange kludges.

I guess I had just expected a more finished product, and I hope I gave them a simple enough example to motivate them to fix the problem.

Bill

— End quote

I think there are only 20 endpoints (8 WireIns, 8 WireOuts, 1 TriggerIn to 16 interrupts, 1 TriggerOut, 1 PipeIn and 1 PipeOut) in my peripheral. I’ve also cleaned up the code quite a bit and there are less than 150 lines of VHDL with any logic.

While it certainly isn’t ideal, adding extra registers, triggers, and even Pipes is fairly straight forward to the structure. Plus, because everything is in a single peripheral, addressing to it within the SDK is very straightforward. I have macros for everything in my sample program that are easy to add to. I wouldn’t call working with it a kludge.

It’s not ideal, but it’s not a kludge.

Garrick

Hi Garrick,

I’m not trying to insult you or any of your work. I think you have done well given what you were handed (although I still havent gotten your version to work yet). I’m mearly saying that Xilinx should not be let off the hook when they have, what looks like to me, serious limitations in their I/O. You shouldn’t have to create a big, combined block, peripheral. You should be able to create something much simpler and more elegant. When you limit the I/O to one peripheral for each port, you defeat the whole purpose of EDK. I might as well just take all the IP and combine it using schematic in ISE or something like that…

What happens if I want more than one pipe?

Obviously, more people will need to run into the same problem before they will fix it. Another thing to note about all this is that it took Xilinx 2 months to finally acknowledge in some way (they kinda just stepped around the admission part) that there is a problem… At this tremendous rate of advancement I’m certainly not holding my breath for a solution from Xilinx…

Bill