Hi, I am desperately trying to figure out an assignment using VHDL. As of right now, I don’t have much of an idea of how to start. I know other programming languages, but VHDL is, of course, more coding instead of programming. To me, VHDL seems somewhat illogical. Nonetheless, I am trying to learn it. I’ve attempted to do a structure, but that seems extremely long and tedious. Thanks in advance. The assignment is as follows:
Use VHDL to design a model of a three port register file. The register file is composed of eight 8-bit registers. The register file has two 8-bit outputs (ports A and B) and a single 8-bit input (port C). Each port has an associated 3-bit address input for selecting one of 8 registers for output (A and B ports) or input (C port). Port C has an associated Clk signal for transferring the input on port C to the addressed register on the falling edge of the Clk signal. Your model should be parameterized to allow the number and bit-width of the register file to be scaled using generic parameters.
Use the following entity definition for the register file:
entity regfile is
generic ( dw : natural := 8;
size : natural := 8;
adrw : natural := 3);
port ( A : out std_logic_vector(dw-1 downto 0);
B : out std_logic_vector(dw-1 downto 0);
C : in std_logic_vector(dw-1 downto 0);
A_adr : in std_logic_vector(adrw downto 0);
B_adr : in std_logic_vector(adrw downto 0);
C_adr : in std_logic_vector(adrw downto 0);
W_Clk : in std_logic);
end entity regfile;