i am a first time user on the "ZEM4310 Opal Kelly"
and i am a bit disappointed. i know that 98% of your device is based on XILINX,
but there is one device of Altera (ZEM4310 ) so i assumed there will be some guide that guide
you step by step .
some examples :
1. were it is written that i need to download *.rbf file ?
2. were it is written that i need to configure the device as "fast passive parallel" ?
3. were it is written that i need to add license to the ?
4. and there is more
and for the Crown jewel, the PCB revision 20121218 have reversed clock
(n is connected to the P and vise versa), this problem can burn the FPGA,
i have a little experience with that.
i ordered the ZEM4310 a couple of weeks ago and i got the 20121218 revision,
instead of the fixed 20131031 revision.
i don't think that i missed something because i read the :
a. Getting Started Guide
b. ZEM4310 User's Manual
c. FrontPanel User's Manual
a few word a bout myself i have experience over 10 years in HDL (XILINX/Altera /Actel)
in Image processing / high speed closed loop system /communication ( modified tcp/ip etc) projects
can someone please clarify this ??
may be there is a document that i forget to read