The PINS reference for the XEM6006 only seems to include the FMC connector pins, not all the pins that are generated in the UCF file. For example, the auto-generated UCF file contains a sys_clk input on FPGA pin T8, but this is not mentioned in the block diagram, user's manual, or PINS reference table.
It's been over a year since the original poster asked the question, but the current version of the manual still does not have the sys_clk information. It is not "documented in the Shuttle LX1 User's Manual" as the reply stated.
Also, the package is shown as FGG256 in the block diagram, and the part is listed as XC6SLX16-2FGG. For the XC6SLX16 the correct package is FTG256, not FGG. It can cause some minor confusion when setting up the Xilinx project.