I’m trying to build the FPGA code for RAMTester on the XEM7310 under Vivado 2019.1.
I created a project and brought in the source files and constraints. I added the MIG IP and customized based on:
I had some initial errors as the fifo IPs were locked and out of date. I upgraded them but now when I try to build it I get:
[Vivado 12-4810] IP ‘fifo_w256_128_r32_1024’ is locked and cannot be converted:
- IP definition ‘FIFO Generator (13.1)’ for IP ‘fifo_w256_128_r32_1024’ (customized with software release 2016.3) has a newer minor version in the IP Catalog. * IP definition ‘FIFO Generator (13.1)’ for IP ‘fifo_w256_128_r32_1024’ (customized with software release 2016.3) has a different revision in the IP Catalog. * Current project part ‘xc7a75tfgg484-1’ and the part ‘xc7a200tfbg484-1’ used to customize the IP ‘fifo_w256_128_r32_1024’ do not match.
I checked and they are updated. I don’t see why the project part is wrong nor where to fix that.