I am trying to port a project from XEM6001 and ISE to XEM7001 and Vivado. I had trouble with the porting, so I decided to try the pipe_test sample program that comes with FrontPanel. Synthesis, implementation, and writing bitfile all run successfully, but with over 200 warnings. Some of them are listed here. No “serious warnings”.
Have I done something wrong that has resulted in these warnings?
(My XEM7001 is on order, so I don’t know if this project works. I only know that all steps were executed successfully.)
[Synth 8-689] width (16) of port connection ‘error_count’ does not match port width (32) of module ‘pipe_in_check’ [“C:/xyz/pipe_test/pipe_test_src/PipeTest.v”:61]
[Synth 8-350] instance ‘mmcm0’ of module ‘MMCME2_BASE’ requires 18 connections, but only 6 given [“C:/xyz/pipe_test/pipe_test_src/okLibrary.v”:56]
[Synth 8-3331] design okBTPipeOut has unconnected port ok1 (99 more like this)
[Vivado 12-4702] SLEW is not a supported property on input port(s). Setting is ignored. [“C:/xyz/pipe_test/pipe_test_src/xem7001.xdc”:30] (7 more line this)
[Constraints 18-96] Setting input delay on a clock pin ‘hi_in’ is not supported, ignoring it [“C:/xyz/pipe_test/pipe_test_src/xem7001.xdc”:65]