Trouble compiling the sample files

FrontPanel
1

hi Jake, when I compile the verilog demo like first.v, controls.v, counter.v, I always get these errors.

ERROR:HDLCompilers:87 - “First.v” line 44 Could not find module/primitive ‘okHostInterface’
ERROR:HDLCompilers:87 - “First.v” line 56 Could not find module/primitive ‘okWireIn’
ERROR:HDLCompilers:87 - “First.v” line 60 Could not find module/primitive ‘okWireOut’
ERROR: XST failed

To fix them, I drag the oklibrary.v file and put it into sources in Project and I still get those errors… :mad: … Please help. Thank you so much…

ps: the VHDL samples complile okay… :confused: …why is it???

2

Is this during the synthesis step?

The okLibrary.v and the *.ngc files that you use should be in your project directory. You can setup options to have them located elsewhere, but it is easiest if they are collocated.

The *.ngc files are required at the implementation step.

3

I have already put those files in the same directory. I still get the same error message.

why did the HDL files compiled but the verilog files didnt???

4

I’m not sure. Has the okLibrary.v file been added to the ISE project? Do the okWireIn and okWireOut modules display under the hierarchy for the toplevel of the design? It works fine for me… Here’s what I did:

  1. Copy the entire folder “XEM3001v2” from the FrontPanel installation to C:.
  2. Open First.ise in ISE 7.1i.
  3. Double-click on “Generate Programming File”

(*)It would seem that there is a typo in the Firsts sample configuration – Under “Implement Design” properties, the Macro Search Path has an extra “” at the end which apparently throws off ISE. This should be removed. However, this does not cause the problem you’re indicating.