I would like to create a top-level schematic of my project, for the benefit of others who cannot read HDL.
I am creating a project based on the ramtest example, except my state machine takes control of the write FIFO on the front end of the sdram controller.
I have tried breaking the HI instantiation into its own module (with the sdram controllers and FIFO’s in another module), and I get compiler errors 26 and 28 depending on exactly how I do it. I can supply more detail if need be, but, since the FP users manual states that the HI must be instantiated in the top level, I realize that I might be trying the impossible.
Is there any way to create a top-level schematic when using Front Panel?
Unfortunately, I’m not sure if this is possible. There are very few people using schematic entry for FPGAs anymore, so I don’t even know how well the tools have been updated.
If this is the only reason you’re producing the top-level schematic, my recommendation would be to produce this schematic for documentation purposes only. There are many arguments against using schematics for the actual design – including (oddly enough) poor documentation capabilities.
I know you didn’t ask for the justification of HDL, but other arguments against schematics are: poor source control, poor tool compatibility and version compatibility, poor maintainability.
Really, maintaining a single top-level schematic for documentation purposes only is a good idea anyhow. Top levels of HDL designs are often just interconnect and can get confusing with the number of named nets required. The overhead in maintaining this is typically less than the difficulty of contorting your design methods to work with a top-level schematic.