I would like to create a top-level schematic of my project, for the benefit of others who cannot read HDL.
I am creating a project based on the ramtest example, except my state machine takes control of the write FIFO on the front end of the sdram controller.
I have tried breaking the HI instantiation into its own module (with the sdram controllers and FIFO’s in another module), and I get compiler errors 26 and 28 depending on exactly how I do it. I can supply more detail if need be, but, since the FP users manual states that the HI must be instantiated in the top level, I realize that I might be trying the impossible.
Is there any way to create a top-level schematic when using Front Panel?