I have an application in which I need to continuously stream data from the FPGA to the PC. My desired throughput is 200MBps. The application runs on windows.
Since I started using the front panel API lately, I’m trying to implement a sandbox application to verify which implementation I should use in order not to lose data.
At the moment I have a 65536 32bit words FIFO in the FPGA which is filled with data ramping from 0 to 0xFFFFFFFF at 50MHz. On the PC side I’m continuously reading the data with ReadFromBlockPipeOut, where block size is 16384 and transfer size is 1048576.
It seems there are no real performance problems, in the sense that the PC receives around 1GB of data every 5 seconds. However, if I check the received data I see that once in a while there is a gap in the expected ramp, and overall I lose about 1-2% of the data.
My best guess is that, since the FIFO fills in about 1.3ms, the OS might let it fill completely if it misses a read for more than 1ms which doesn’t seem impossible, so my next try would be to use the DDR RAM on the board in place of the FIFO in order to better buffer the data.
Does anyone have a better solution or sees any problem with what I’m doing?
Thank you in advance for your help