I use the xem3005, fw 3.1 on the ubuntu linux platform. I use several of your hdl modules (Wire, Trigger and BTPipe) in my fpga implementation. The FPGA interfaces with our own ASICs and I store the replies from the ASICs in a FIFO (generated by the coregen as you recommend) before a fetch the results back to the PC using a BTPipeOut module. My software is written in Java using Eclipse.
The problem is that the amount of data stored in the FIFO might vary and it might be impossible to predict how much data that is located in the FIFO. I use the ready flag is connected to a programmable empty flag in the FIFO and is asserted when there is data available for one transfer.
I want to flush the FIFO and my my approach is to keep asking for data untill the FIFO is empty. This is a problem though, since the API freezes if the ready flag is deasserted - The method call and never timeout’es. I’ve tried to set the timeout value in the API, but it seems that this timeout value is not applied in the ReadFromBTPipeOut method.
From my own experiences with the CY68013A IC I recall that it was possible to ask for “too much” data and simple use the returned length value to figure out how much data was really returned. Is this not possible with FrontPanel?
Do I have to implement a parallel data count functionality?
Thanks in advantage