Problem with linking Xilinx cells instantiated in okHost.vhd


In synthesis (including the Opal Kelly library,) I am getting this warning:

HDLCompiler:89 - “C:\Users\somebody\projects\cool_project\okLibrary.vhd” Line 40: remains a black-box since it has no binding entity.

Line forty in okLibrary.vhd is the start of this component declaration:

component FDRE port (
D : in std_logic;
C : in std_logic;
CE : in std_logic;
R : in std_logic;
Q : out std_logic);
end component;
attribute iob of FDRE : component is “TRUE”;

Further on in okLibrary.vhd, I see these instantiations:

       fdrein0:  FDRE port map(D=>iodly0_datain(i), C=>ti_clk_int, CE=>'1', R=>'0', Q=>hi_datain(i));
       fdreout0: FDRE port map(D=>okCH(i+3), C=>ti_clk_int, CE=>'1', R=>'0', Q=>fdreout0_hi_dataout(i));
       fdreout1: FDRE port map(D=>not_okCH2, C=>ti_clk_int, CE=>'1', R=>'0', Q=>fdreout1_hi_drive(i));

Is there anything else I need to do in ISE, in order to get these cells linked in successfully? What will happen if these are absent from the resulting netlist?

(I am targeting a Spartan6 family device, XC6SLX150. I’m using the XST synthesis tool (in ISE) and using VHDL. This is all with ISE Project Navigator, Release 14.7 (nt64), Application version P.20131013.)

Thanks for any help or suggestions.