Performance: Is there any performance degredation/hit if all endpoints were setup

Performance question regarding FrontPanel:

I want to create a generic OK interface module instantiating all wirein/wireout/triggerIn and triggerOut endpoints, but may only use a subset in the HDL design and conversely only communicate with that same subset from the SW end. Is there a performance hit to the communication between the sSW and the OK interface on the FPGA?

Thanks for any insight on this. I’d like to start using more generic templates if possible.



This generally shouldn’t be a problem. Xilinx XST will prune those items that you don’t use at build time.

Thanks for the reply.

The manual says that UpdateTriggerOuts updates ALL of the trigger out values from the FPGA at the same time. Will the USB overhead of UpdateTriggerOuts be increased if my design has more Trigger Outs? In the extreme if I instantiated all 32 of the Trigger Outs, would it take longer to UpdateTriggerOuts than if I only have one Trigger Out instantiated?

I am working on a project that streams data over the USB and I need to periodically check the status of the FPGA. Some of the status indicators need to be TriggerOuts so that I can detect brief events that I might miss by polling a WireOut. Currently the design uses a combination of Wire Outs and Trigger Outs for status indicators. Would it be more efficient to use all Trigger Outs and eliminate the call to UpdateWireOuts?

I am using XEM6001.

The following calls are performed atomically in the context of communication over USB:

Therefore, for the “Update” calls, a single USB transaction is performed to complete the call regardless of the number of wires or triggers actually instantiated in your design.