Performance question regarding FrontPanel:
I want to create a generic OK interface module instantiating all wirein/wireout/triggerIn and triggerOut endpoints, but may only use a subset in the HDL design and conversely only communicate with that same subset from the SW end. Is there a performance hit to the communication between the sSW and the OK interface on the FPGA?
Thanks for any insight on this. I’d like to start using more generic templates if possible.