Newbie issue: a pipe setup problem with XEM7350?


Good Morning,
I’ll buy a coffee for the solution. :slight_smile:

This is my first activity with the XEM7350, and I seek to have a simple GUI on the PC running so that I can click four buttons and have 4 bits on the FMC follow along with a hi/lo logic level.

To validate my connectivity and to demonstrate control through the FPGA, I’ve added a 4 bit LedReg register, initialized it to a 1010 pattern, and observed that LED0 and LED2 are illuminated on the XEM7350 when I load the .bit file via FrontPanel.

But I don’t get that “test pattern” showing up on the FMC or the status indicators on the GUI.

The Verilog .v is below, I can also post the .ucf file, the .xfp file and screenshots of the ISE project Navigator, FrontPanel, the GUI I made, and the settings for the XEM7350 if that would help to diagnose my situation.


`timescale 1ns / 1ps
// Company:
// Engineer:
// Create Date:    08:16:16 16SEP2015
// Design Name:
// Module Name:    Main_For4
// Project Name:
// Target Devices:
// Tool versions:
// Description:
// Dependencies:
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
module Main_For4(
// the PC is the Host - the FPGA is the target - Endpoints are in the target
// HE - Host to Endpoint control signals
// EH - Endpoint to Host control signals
// UH - Host interface input signals
// HU - Host interface output signals.
// UHU - Host interface bidirectional signals
// AA  - Host interface bidirectional signals

input wire [2:0] okHU,
    input wire [4:0] okUH,
    inout wire [31:0] okUHU,
    inout wire okAA,
    output wire [3:0] led,
    output wire FMC_H7,
    output wire FMC_H8,
    output wire FMC_G9,
    output wire FMC_G10
//FMC was inout
Extract from xem7350.ucf

// Target interface bus:  this is to the FPGA from the interface from the USB
wire okClk;         // ti_clk; renamed 11SEP2015
wire [112:0] okHE;  //ok1; renamed 11SEP2015
wire [64:0] okEH;   //ok2; renamed 11SEP2015
wire [3:0] FMC_status; //removed “output” 21JUL2015

// Endpoint connections:  this is within the FPGA
wire [31:0] ep00wire;
wire [31:0] ep20wire;

//mtr 21JUL2015 - figure out how to save the bits for output
reg [3:0] BitsOut;
reg [3:0] LedReg;
//for debug support activity
initial LedReg = 4’b1010;  //0 turns on an LED, 1 turns it off

//assign led[0] = ep00wire[0];
//assign led[1] = ep00wire[1];
//assign led[2] = ep00wire[2];
//assign led[3] = ep00wire[3];
assign led[0] = LedReg[0];  //0 turns on an LED (1.8v is present at far end of LED, 0v at close end)
assign led[1] = LedReg[1];  //1 turns it off (3.3v is present at both ends of LED)
assign led[2] = LedReg[2];
assign led[3] = LedReg[3];

// Instantiate the okHost and connect endpoints.
//taken from FrontPanel-UM.pdf, and modified - mtr
okHost okHI (.okUH(okUH), .okHU(okHU), .okUHU(okUHU), .okAA(okAA), .okClk(okClk), .okHE(okHE), .okEH(okEH));
okWireIn ep00 (.okHE(okHE), .ep_addr(8’h00), .ep_dataout(ep00wire));
okWireOut ep20 (.okHE(okHE), .okEH(okEH), .ep_addr(8’h20), .ep_datain(ep20wire));

always @(posedge ep00wire[4])
  BitsOut[0] <= ep00wire[0];
  BitsOut[1] <= ep00wire[1];
  BitsOut[2] <= ep00wire[2];
  BitsOut[3] <= ep00wire[3];
  LedReg[0] = !LedReg[0];
  LedReg[1] = !LedReg[1];
  LedReg[2] = !LedReg[2];
  LedReg[3] = !LedReg[3];
//assign FMC_H7 = BitsOut[0];
//assign FMC_H8 = BitsOut[1];
//assign FMC_G9 = BitsOut[2];
//assign FMC_G10 = BitsOut[3];
// next four are testcase items
assign FMC_H7 = LedReg[0];
assign FMC_H8 = LedReg[1];
assign FMC_G9 = LedReg[2];
assign FMC_G10 = LedReg[3];

//mtr - define the return values - 21JUL2015
assign FMC_status[0] = FMC_H7;
assign FMC_status[1] = FMC_H8;
assign FMC_status[2] = FMC_G9;
assign FMC_status[3] = FMC_G10;
//mtr - continue to define the return values - 21JUL2015
assign ep20wire[0] = FMC_status[0];
assign ep20wire[1] = FMC_status[1];
assign ep20wire[2] = FMC_status[2];
assign ep20wire[3] = FMC_status[3];



At the behest of the OK support staff, I checked the operation of the “counters” example. That was fine. I did a side by side code comparison, and quickly saw that what should be “output wire [2:0] okHU” was an input.

I won’t do that again!