I replied to your support email as well but am posting here for the benefit of others.
The problem most likely is the setting for the FPGA Start-up clock. Under ISE, the default start-up clock is CCLK (which is required for FrontPanel configuration). If you compile through the EDK, it defaults the start-up clock to the JTAG clock because that’s what they assume you are using. I’m not sure if you can change this setting easily in the EDK. If you figure out how to, let us know.
I know there is a way in Impact to modify a compiled .bit file to change the startup-clock option, and of course in ISE, you can right click “Generate Programming File->Properties” and then select “Startup Options” to set the start-up clock to whatever you want.
Maybe Xilinx knows of a slick way to set this in the EDK 8.2. I setup the MicroBlaze tutorial a while ago under EDK 8.1, so I haven’t investigated the differences in 8.2. I guess there is better integration between the different software packages.