How works pipetest?


I have difficulties to understand how pipetest works.
In the documentation , the IPCore WireIn gives a data configuration for the device.But how can I access to these data because I only have the signal ep_dataout which is 16 bits long but no address as a memory to select the address.
Is the WireIn a 16 bits word or longer?
What is the size of the WireIn?
Could you explain me how does it work and how can I access it?
Thank you


The data from the PipeIn and PipeOut EP’s are not stored or available in any memory device or array, it is simply streamed in. The Buffered PipeIn and Buffered PipeOut store data in FIFOs. You can create your own storage module by writing a logic block that connects a pipe HDL module to a custom FIFO or some other memory construct.

The data for the Pipes must be either stored or processed as it streams into (or out of) a 16-bit wide wire. For instance, in PipeTest every time a 16-bit word is “piped” into EP 0x80 it is xor’ed into a local register, pipeI_xor. This local register is updated with a new value from the pipeIn at every ti_clk that pipeI_write signal (input from the PipeIn) is high.

I hope that helps a little at least.