How to set PLL for SDRAM?


Hi there,

Now I need 133MHz clock signal for SDRAM on-board(XEM3010). According to OpalKelly user guide, VCO must be less than 400MHz (ref=48MHz), and DIV can not be greater than 4. That means the highest frequency we can get is 100MHz. But XEM3010 UM says it supports upto 150MHz clock output.
So I just wonder how can i get it and or SDRAM need different clock reference in this case?




First, I should note that the User’s Manual documentation was written for the 22150. Oddly enough, you’re the first to mention this deficiency and we never noticed it, so we’ll have to make some changes.

The 22150 has a DIV limit of 4, but has some selectors which allow you to select different dividers rather than DIV1, DIV2. This allows you to go past the 100 MHz, just not using DIV1 or DIV2.

The XEM3010 has a 22393 on it which provides some different configuration. In particular, you can select a divider independently for each output. Additionally, the divider has a range of 1-127. So just set Div=3 with 400 MHz VCO frequency and you’ll have 133.333 MHz on output.

The CY22393 datasheet is included in the “Extras” directory of your FrontPanel installation CD. Our PLL C++ class abstracts the configuration a bit, but doesn’t do all the math – it mostly provides easy access to the parameters available.

The PLL configuration dialog within the FrontPanel Application will let you see what output frequency is chosen for a given set of parameters. This can help a bit in selecting the right dividers.

Cypress provides an application called CyClocks which does a more thorough approach by letting you choose a frequency, then it will compute the parameters required to get as close as possible to your target frequency. Certainly not necessary for your 133 MHz, but it can come in handy for some obscure frequencies like audio sample rates and so on.