HostInterface problem

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1

Hi,
I am getting errors trying to implement VHDL project with latest firmare, specifically with HostInterface and ok2() bus.

FIRST:

use IEEE.STD_LOGIC_1164.ALL;
entity okHostInterfaceCore is
port (
hi_in : in std_logic_vector(7 downto 0);
[COLOR=“Red”]hi_out : out std_logic_vector(2 downto 0);[/COLOR]
hi_datain : in std_logic_vector(15 downto 0);
hi_dataout : out std_logic_vector(15 downto 0);
ok1 : out std_logic_vector(30 downto 0);
ok2 : in std_logic_vector(16 downto 0)
);
end okHostInterfaceCore;

However, only hi_out(0) - FPGA pin V10 and hi_out(1) - FPGA pin V11 are mentioned in the latest XEM3010 Quick Reference manual.

Where is hi_out(2) ?

SECOND:

okWireIn, okWireOut, etc. all have

ok2 : out std_logic_vector(16 downto 0);

defined as [COLOR=“Red”]out[/COLOR]_std_vector. I am having problem when busing multiple endpoints…

Pleaselet me know if I am doing something wrong and how to resolve these.

Thanks,
Vlad

2

Vlad –

Your logic should be instantiating okHostInterface (okHostInterfaceCore).

3

OK, thanks!

I fixed that, but how about the SECOND problem - collision on ok2() when multiple endponts are bussed together? There must be some mechanism to tri-state all unselected endpoints.

Thanks

4

I’m not sure why you are having any collision. All of our samples have multiple endpoints defined and share ok2.