I’m using a XEM6310-LX45 with FrontPanel 4.2.5, and I’m having a very strange behavior. My design include a memory controller with an input FIFO from my logic and an output FIFO to a BlockPipeOut (very similar to the sample design). Since my logic produce data in real time (I can not stop data flow), I monitor the fifo_full flags and the memory, to be sure no data is lost during the transfer. When I connect the board in USB 2.0 mode (i.e. using a a USB 2.0 cable), FrontPanel sees it as a USB 2.0 device, and everything works fine: I got a “data loss” error only when the data generation rate of my logic exceed about 35MB/s. Instead, with the same PC and the same bitfile, if I connect the board in USB 3.0 mode (properly recognized by FrontPanel), I got “data loss” error at a much lower data generation rate. To make things more strange, the error is generated by the input FIFO, which is in the inner part of the design and is not clocked by ti_clk (as instead fifo out is). The same behavior occurs on Windows 8-x64, Windows 7-x64 and Mac OS X Mavericks. Any thought about that? What changes in FrontPanel HDL endpoint when connection is made in USB 2.0 or 3.0 mode? Could it be that wires are updated too fast with USB 3.0?
…maybe I found a possible explanation. The RAM controller, that was originally developed for a XEM6010, gives priority to memory reading. USB 3.0 is much faster than USB 2.0, thus when I call a large reading from the pipe it actually stucks the controller in the read state, blocking any write from the fifo in. I will now modify the design to see if I’m right.