|
Alternative Clock inputs (e.g. to XEM6310MT-LX45T via BRK6310MT breakout board)
|
|
0
|
801
|
December 16, 2019
|
|
okFrontPanel library causes Matlab to crash sometimes
|
|
5
|
1642
|
December 14, 2019
|
|
DLL import location for libokFrontPanel.dylib
|
|
10
|
2100
|
November 16, 2019
|
|
LX6 on a XEM7310 FPGA
|
|
0
|
710
|
October 30, 2019
|
|
ReadFromPipeOut - latency support
|
|
1
|
964
|
September 15, 2019
|
|
C# memory management with ReadFromBlockPipeOutX
|
|
0
|
767
|
September 11, 2019
|
|
Using Xilinx IP Integrator Designs with FrontPanel
|
|
0
|
761
|
June 4, 2019
|
|
Shuttle LX1 (XEM6006) 12V to FMC
|
|
0
|
913
|
July 2, 2019
|
|
25ms delay in WriteToPipeIn
|
|
6
|
891
|
July 1, 2019
|
|
ReadFromBlockPipeOut(...) times out on large reads
|
|
8
|
2868
|
June 30, 2019
|
|
RegisterBridge with data loss
|
|
1
|
1782
|
June 20, 2019
|
|
KiCad resources
|
|
0
|
826
|
June 16, 2019
|
|
OK FrontPanel HDL to AXI Master
|
|
2
|
2729
|
June 6, 2019
|
|
XEM7360 VADJ values not settable
|
|
3
|
2328
|
June 4, 2019
|
|
LabView Interface with XEM6010 and XEM6006
|
|
1
|
1994
|
June 4, 2019
|
|
XEM7360: Setting VADJ without FrontPanel
|
|
0
|
701
|
June 4, 2019
|
|
Best language/API to interface with FPGA/Front Panel?
|
|
1
|
1383
|
May 23, 2018
|
|
ISE gives error for okHostCalls.v
|
|
3
|
1797
|
May 1, 2019
|
|
OK Reserved FPGA pins
|
|
1
|
711
|
May 25, 2019
|
|
XEM7360 USB3.0 and Microblaze
|
|
0
|
873
|
May 17, 2019
|
|
FrontPanel with Python 3.7
|
|
1
|
968
|
April 29, 2019
|
|
hi_muxsel specification
|
|
2
|
2364
|
April 24, 2019
|
|
FrontPanel explanation
|
|
2
|
941
|
April 15, 2019
|
|
XEM6001 not compatible with WebPack license?
|
|
3
|
2550
|
April 28, 2016
|
|
MIG simulation on XEM7310
|
|
0
|
1037
|
March 14, 2019
|
|
Failing okHostIN_grp timing constraint on xem6310
|
|
3
|
1010
|
February 5, 2019
|
|
ActivateTriggerIn() via C++
|
|
4
|
2227
|
December 12, 2016
|
|
OpalKelly licenses for encrypted HDL modules?
|
|
2
|
1915
|
January 25, 2019
|
|
XEM7305 DDR3 MIG BA0 wrong pin?
|
|
1
|
1153
|
January 7, 2019
|
|
Running into "All Address/Control ports should be selected in a single bank. Address/Control selected Banks: 15. To bypass this error and proceed further for design generation" Error when generating DDR3 controller on XEM7310
|
|
0
|
906
|
January 17, 2019
|