VHDL / Verilog Discussion


Topic Replies Activity
Transferring Data using Verilog and Python 2 June 23, 2017
Verilog Initial begin does not execute in simulation 1 July 2, 2014
Difference between Bit File and UCF File 1 April 2, 2014
Problem VHDL help in code please 1 January 24, 2014
beginner question 1 November 7, 2013
beginner question 1 November 7, 2013
OK HOST - bus interfacing - vhdl vs verilog - different implementation - question 4 November 5, 2013
Verilog beginner question 2 November 5, 2013
Outputting Clock 1 August 15, 2013
VHDL Help - Controlling A Stepper Motor Driver 1 July 26, 2013
ActivateTriggerIn Simulation task 2 May 8, 2013
VHDL: Register File with Eight 8-bit Registers 1 February 22, 2013
URGENT, Need Help in Verilog code! 1 July 7, 2012
Trouble with ISE 13.2 and wireIn/wireOut ngc files 4 February 2, 2012
Need guideline for NRZI output related question 1 September 11, 2011
Visualize your design with Robei 1 April 26, 2011
Need some vhdl help 2 December 10, 2010
Factors req to choose VHDL or Verilog 3 November 30, 2010
Source files encrypiton 1 February 9, 2010
Verilog Constructs 3 November 18, 2009
Uart 1 March 8, 2009
C to Verilog 1 December 16, 2008
OK and synplicity synthesis tool 2 December 12, 2008
A new FPGA design tutorial 1 December 8, 2008
8051 with watchdog timer 1 July 14, 2008
Expression unsynthesizable 2 June 17, 2008
Dividision by repeted multiplication 3 May 22, 2008
VHDL not seeing output port 2 May 20, 2008
Vhdl code error 2 May 17, 2008
Timing issues ! help help! 1 May 8, 2008