Hi,
I’m currently working on implementing a FIFO using the on-board RAM chip available on the XEM6010-LX45 module. The purpose of this FIFO is to provide a buffer for streaming data to PC from a high-speed data sampling system, since the FPGA fabric does not provide sufficient space for buffering data between reads. My implementation is based loosely off the sample provided by Opal Kelly, with the main difference being that I’m using two 32-bit ports rather than one in order to allow simultaneous reading and writing, as well as logic for keeping track of the amount of data in the FIFO and providing status indicators (full, empty, etc.).
I’m testing the FIFO module by simply writing in the sequence of natural numbers (0, 1, 2, 3, …), then reading it out again and comparing the output values to the inputs. For the most part it works as expected, but I’m having a few issues that I’m hoping someone here could help me with.
The biggest issue I’m having is that, occasionally (<0.5% of the time), the same value will be output three times in a row (never two and never more than three). It overwrites the expected values, rather than ‘pushing’ them along the stream; for example:
Inputs: 0, 1, 2, 3, 4, 5, 6, 7, 8, …
Outputs: 0, 1, 2, 3, 4, 4, 4, 7, 8, …
As you can see, the value ‘4’ has overwritten ‘5’ and ‘6’, but the next value ‘7’ is in the expected place. Each value is 32-bits. It appears to happen more often when using a faster clock; currently I’m only clocking the memory at 250 MHz. The same issue occurs on two different XEM6010-LX45 devices, one of which was brand new, so I’ve ruled out damage to the device.
Has anyone got any suggestions as to what I might be doing wrong? I’m not terribly experienced with using RAM at this level, so I’m probably missing something obvious. All help is very much appreciated - thanks!