Hi,
I tried to have to attached design work on xem 3005. Problem, when i upload bitstream, ti_clk is stucked… Any idea ? ( design is very simple… )
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.FRONTPANEL.all;
use work.TB3_pack.all;
use work.Sirius_Pack.all;
entity BTS3 is
port (
hi_in : in STD_LOGIC_VECTOR(7 downto 0);
hi_out : out STD_LOGIC_VECTOR(1 downto 0);
hi_inout : inout STD_LOGIC_VECTOR(15 downto 0);
i2c_sda : out STD_LOGIC; i2c_scl : out STD_LOGIC; hi_muxsel : out STD_LOGIC;
Clk : in std_logic;
---------------------- -- Sirius 3 interface ----------------------
S3_Reset_n : out std_logic; S3_Clk : out std_logic;
S3_Din : out std_logic; S3_Dout : in std_logic; S3_Trig_I : out std_logic; S3_Trig_O : in std_logic;
-- ADC
S3_ADC_sel : out std_logic_vector(1 downto 0); S3_DADC_test : out std_logic; S3_Aready : in std_logic; S3_Start : out std_logic; S3_ADout : in std_logic_vector(13 downto 0);
-- Debug
S3_FSM_Error : in std_logic;
---------------------- -- SPI bus ----------------------
SPI_Sck : out std_logic; SPI_Data : out std_logic; SPI_CS_Th_n : out std_logic; SPI_CS_DAC_n : out std_logic;
---------------------- -- Debug ----------------------
Button : buffer STD_LOGIC_VECTOR(3 downto 0); Led : buffer STD_LOGIC_VECTOR(7 downto 0);
---------------------- -- SV1 ----------------------
SV1_Din : out std_logic; SV1_Dout : out std_logic; SV1_CLK : out std_logic; SV1_TRIG_I : out std_logic; SV1_TRIG_O : out std_logic; SV1_Reset_n : out std_logic; SV1_fsm_error : out std_logic; SV1_L4 : out std_logic;
---------------------- -- SV2 ----------------------
SV2_Adout7 : out std_logic; SV2_Adout6 : out std_logic; SV2_Adout5 : out std_logic; SV2_Adout4 : out std_logic; SV2_Adout3 : out std_logic; SV2_Adout2 : out std_logic; SV2_Adout1 : out std_logic;
---------------------- -- SV3 ----------------------
SV3_Aready : out std_logic; SV3_Start : out std_logic; SV3_Adout13 : out std_logic; SV3_Adout12 : out std_logic; SV3_Adout11 : out std_logic; SV3_Adout10 : out std_logic; SV3_Adout9 : out std_logic; SV3_Adout8 : out std_logic;
---------------------- -- SV4 ----------------------
SV4_Dadc_test : out std_logic; SV4_adc_sel0 : out std_logic; SV4_adc_sel1 : out std_logic; SV4_adout0 : out std_logic; SV4_SPI_CS_TH_n : out std_logic; SV4_SPI_CS_DAC_n : out std_logic
);
end BTS3;
architecture Behavioral of BTS3 is
signal Reset, Reset_n : std_logic;
– Host interface connections
signal ti_clk : STD_LOGIC;
signal ok1 : STD_LOGIC_VECTOR(30 downto 0);
signal ok2 : STD_LOGIC_VECTOR(16 downto 0);
signal ok2s : STD_LOGIC_VECTOR(17*3-1 downto 0);
signal ep00wire : STD_LOGIC_VECTOR(15 downto 0);
– Version
signal version : std_logic_vector(15 downto 0);
– Sirius 3
signal Din : std_logic;
signal Dout : std_logic;
signal Trig_I : std_logic;
signal Trig_O : std_logic;
signal ADC_sel : std_logic_vector(1 downto 0);
signal DADC_test : std_logic;
signal Aready : std_logic;
signal Start : std_logic;
signal ADout : std_logic_vector(13 downto 0);
signal FSM_Error : std_logic;
– TC
signal status : std_logic;
signal Command : std_logic_vector(15 downto 0);
signal Trame : std_logic_vector(0 to 31);
signal Cmd01 : std_logic_vector(15 downto 0);
signal Cmd23 : std_logic_vector(15 downto 0);
signal n : integer range 0 to 32;
– ADC
signal ADC_Conf : std_logic_vector(15 downto 0);
signal ADC_Value : std_logic_vector(15 downto 0);
– FIFO
signal TM_FIFO_Bc : STD_LOGIC_VECTOR(12 downto 0);
signal TM_FIFO_Din : STD_LOGIC_VECTOR(15 downto 0);
signal TM_FIFO_Wr : std_logic;
signal TM_FIFO_Dout : STD_LOGIC_VECTOR(15 downto 0);
signal TM_FIFO_Rd : std_logic;
signal TM_FIFO_Empty : std_logic;
signal TM_FIFO_Full : std_logic;
– FSM
type state_type is ( S_Idle, S_Send_Cmd );
signal current_state : state_type;
signal CONTROL : STD_LOGIC_VECTOR(35 DOWNTO 0);
signal TRIG0 : STD_LOGIC_VECTOR(7 DOWNTO 0);
begin
–
– Opal Kelly stuff…
Reset_n <= not Command(0); Reset <= Command(0);
i2c_sda <= 'Z'; i2c_scl <= 'Z';
hi_muxsel <= '0';
led(0) <= ti_clk; led(1) <= not Cmd01(0); led(2) <= not Cmd01(1); led(3) <= Clk; led(7 downto 4 ) <= ( others => '1' );
-- Instantiate the okHostInterface and connect endpoints to the target interface.
okHI : okHost port map (hi_in=>hi_in, hi_out=>hi_out, hi_inout=>hi_inout, ti_clk=>ti_clk, ok1=>ok1, ok2=>ok2); okWO : okWireOR generic map (N=>3) port map (ok2=>ok2, ok2s=>ok2s);
-------------------------------------------------------------------------- -- Command register --------------------------------------------------------------------------
tr40 : OkTriggerIn port map ( ok1 => ok1, ep_addr => x"40", ep_clk => Clk, ep_trigger => Command );
-------------------------------------------------------------------------- -- Sirius 3 TC : 4 bytes --------------------------------------------------------------------------
wi01 : okWireIn port map ( ok1 => ok1, ep_addr => x"01", ep_dataout => Cmd01 );
wi02 : okWireIn port map ( ok1 => ok1, ep_addr => x"02", ep_dataout => Cmd23 );
-------------------------------------------------------------------------- -- Sirius 3 ADC interface --------------------------------------------------------------------------
wo21: OkWireOut port map ( ok1 => ok1, ok2=>ok2s( 1*17-1 downto 0*17 ), ep_addr => x"21", ep_datain => ADC_Value );
wi03 : okWireIn port map ( ok1 => ok1, ep_addr => x"03", ep_dataout => ADC_Conf );
-------------------------------------------------------------------------- -- Sirius 3 TM --------------------------------------------------------------------------
epA0 : okPipeOut port map ( ok1 => ok1, ok2 => ok2s(2*17-1 downto 1*17 ),ep_addr => x"a0", ep_read => TM_FIFO_Rd, ep_datain => TM_FIFO_Dout );
ep22 : okWireOut port map ( ok1 => ok1, ok2 => ok2s(3*17-1 downto 2*17 ), ep_addr=>x"22", ep_datain=>version );
version <= x"B00A";
–
– TM/TC FIFOs
–TM_FIFO : FIFO_32kx16 port map(
– rst => reset,
– wr_data_count => TM_FIFO_Bc,
– empty => TM_FIFO_Empty,
– full => TM_FIFO_Full,
– wr_clk => Clk,
– wr_en => TM_FIFO_Wr ,
– din => TM_FIFO_Din,
– rd_clk => ti_clk,
– rd_en => TM_FIFO_Rd,
– dout => TM_FIFO_Dout
–);
–
– Sirius 3
S3_Reset_n <=‘0’;
S3_Clk <= ‘0’;
S3_Din <= Din;
S3_Trig_I <= Trig_I;
S3_ADC_sel <= ( others => ‘0’);
S3_DADC_test <= DADC_Test;
S3_Start <= ‘0’;–
– ADC management
ADC_Sel <= ADC_Conf(1 downto 0); – Dolphin ou IRAP
DADC_test <= ADC_Conf(2);
Start <= Command(7);
ADC_Value <= not Aready & ‘0’ & S3_ADout;
–
– Pipe to sirius 3
P3s: process(Reset_n, Clk) begin if reset_n ='0' then
S3_Reset_n <='0'; current_state <= S_Idle;
Din <= '0'; n <= 0; status <= '1';
else if clk='0' and clk'event then
case current_state is
when S_Idle => Din <= '0'; if Command(1) = '1' then Trame <= Cmd01 & Cmd23; -- 16 - 16 n <= 0; current_state <= S_Send_Cmd; end if;
when S_Send_Cmd => Din<= Trame(n); n <= n + 1; if n >= 31 then current_state <= S_Idle; status <= not status; end if;
when others => current_state <= S_Idle;
end case; end if; end if;
end process;
–
– SPI DAC
SPI_Sck <= ‘0’;
SPI_Data <= ‘0’;
SPI_CS_Th_n <= ‘0’;
SPI_CS_DAC_n <= ‘0’;
–
– SPI thermometer
end Behavioral;