I’m designing a test-bench using the VHDL template you give, and having writing my own procedures to mimic the behaviour of my software; similar to the way you simulate the OK functions.
For the VHDL version, you say to COPY & PASTE the okHostCalls_vhd.txt into the test-bench fixture as one cannot use an external file like in the verilog version.
I’ve just been reading about PROCEDURES, the VHDL book states at procedures and functions can reside in two places:
the main code - as per your method
in a PACKAGE - equivalent to how you do it in verilog?
It seems to me that you could re-write the VHDL test-bench using a PACKAGE for all the okHost calls.