VHDL ramtest XEM3010

Contributions
1

I translated the verilog top module to VHDL for anyone that was having problems or just to save time. The controller is still in verilog. I am using Xilinx Webpack 9.2. I just used the same C++ executable as previous example to test it. It ran fine 100 passes no fails.

RAMTEST VHDL.zip (107.2 KB)

2

Thanks, phil126!!

3

Hi,

I am having difficulties reading the RAMTEST zip file…has anybody else suffered the same problem???

Regards

Dave

4

Works fine here – using FireFox / Windows.

5

I’ve sorted it…I was double clicking on the downloaded file…rather than right clicking the mouse and selecting an option…

Thanks

6

:confused:Hi,

I 've been trying to run the vhdl test ram file, but when I open the file, there are only a bunch of characters (imposible to read). If someone knows how to open it, use it or can email it to me, I will highly appreciate his/her help.

cheers,
rfr

7

I too am having trouble opening the file (107,151 bytes), using either
Winzip Pro 11.1 or ‘Compressed folders’ in XP Pro SP3.

Both apps report that the file is not a valid archive.

Richard ST

8

Please try using Firefox, Opera, Safari, or any other non-IE browser to download from the forums. That may fix the problem.

9

I downladed and installed Firefox. It took about 2 minutes.
Browsed here + downloaded the file (109,757 bytes). 2 minutes.

Maybe I don’t know what I’ve been missing by sticking with IE. Thanks for your help.

Richard

10

— Begin quote from phil126;1735

I translated the verilog top module to VHDL for anyone that was having problems or just to save time. The controller is still in verilog. I am using Xilinx Webpack 9.2. I just used the same C++ executable as previous example to test it. It ran fine 100 passes no fails.

— End quote

Hi Phil126,

could you explain why your okWireIn instantiation has a ok2 port? All the examples I’ve seen use something like:

ep00 : okWireIn port map (ok1=>ok1, ep_addr=>x"00", ep_dataout=>ep00wire);

11

His version was written with an older version of the HDL modules. The newer version is slightly different in how it handles the shared bus ports:

http://wiki.opalkelly.com/frontpanel3p1deltas

12

The link for the zip no longer seems to be active.