can anyone tell me if there are any errors in this code or how it can be simplified?? thank you guys,
module dcpu16_mbus (/AUTOARG/
// Outputs
g_adr, g_stb, g_wre, f_adr, f_stb, f_wre, ena, wpc, regA, regB,
// Inputs
g_dti, g_ack, f_dti, f_ack, bra, CC, regR, rrd, ireg, regO, pha,
clk, rst
);
// Simplified Wishbone
output [15:0] g_adr;
output g_stb,
g_wre;
input [15:0] g_dti;
input g_ack;
// Simplified Wishbone
output [15:0] f_adr;
output f_stb,
f_wre;
input [15:0] f_dti;
input f_ack;
// internal
output ena;
output wpc;
output [15:0] regA,
regB;
input bra;
input CC;
input [15:0] regR;
input [15:0] rrd;
input [15:0] ireg;
input [15:0] regO;
input [1:0] pha;
input clk,
rst;
/AUTOREG/
// Beginning of automatic regs (for this module’s undeclared outputs)
reg [15:0] f_adr;
reg f_stb;
reg f_wre;
reg [15:0] g_adr;
reg g_stb;
reg [15:0] regA;
reg [15:0] regB;
reg wpc;
// End of automatics
reg wsp;
reg [15:0] regSP,
regPC;
assign ena = (f_stb ~^ f_ack) & (g_stb ~^ g_ack); // pipe stall
// repeated decoder
wire [5:0] decA, decB;
wire [3:0] decO;
assign {decB, decA, decO} = ireg;
/*
0x00-0x07: register (A, B, C, X, Y, Z, I or J, in that order)
0x08-0x0f: [register]
` 0x10-0x17: [next word + register]
0x18: POP / [SP++]
0x19: PEEK / [SP]
0x1a: PUSH / --SP]
0x1b: SP
0x1c: PC
0x1d: O
0x1e: [next word]
0x1f: next word (literal)
0x20-0x3f: literal value 0x00-0x1f (literal)
*/
// decode EA
wire Fjsr = (ireg [4:0] == 5’h10);
wire [5:0] ed = (pha[0]) ? decB : decA;
wire Eind = (ed[5:3] == 3’o1); // [R]
wire Enwr = (ed[5:3] == 3’o2); // [PC++] + R]
wire Epop = (ed[5:0] == 6’h18); // [SP++]
wire Epek = (ed[5:0] == 6’h19); // [SP]
wire Epsh = (ed[5:0] == 6’h1A); // --SP]
wire Ersp = (ed[5:0] == 6’h1B); // SP
wire Erpc = (ed[5:0] == 6’h1C); // PC
wire Erro = (ed[5:0] == 6’h1D); // O
wire Enwi = (ed[5:0] == 6’h1E); // [PC++]
wire Esht = ed[5]; // xXX
wire [5:0] fg = (pha[0]) ? decA : decB;
wire Fdir = (fg[5:3] == 3’o0); // R
wire Find = (fg[5:3] == 3’o1); // [R]
wire Fnwr = (fg[5:3] == 3’o2); // [PC++] + R]
wire Fspi = (fg[5:0] == 6’h18); // [SP++]
wire Fspr = (fg[5:0] == 6’h19); // [SP]
wire Fspd = (fg[5:0] == 6’h1A); // --SP]
wire Frsp = (fg[5:0] == 6’h1B); // SP
wire Frpc = (fg[5:0] == 6’h1C); // PC
wire Fnwi = (fg[5:0] == 6’h1E); // [PC++]
wire Fnwl = (fg[5:0] == 6’h1F); // PC++
// PROGRAMME COUNTER - loadable binary up counter
reg [15:0] rpc;
reg lpc;
always @(posedge clk)
if (rst) begin
/AUTORESET/
// Beginning of autoreset for uninitialized flops
regPC hX;
end
endmodule // dcpu16_mbus