Does the TriggerOut connection in HDL require a level change or a pulse?
From the okTriggerOut documentation in the FrontPanel User’s Manual (emphasis added):
[QUOTE]The target may trigger the host using this module. EP_TRIGGER[31:0] contains 32 independent
trigger signals which are monitored with respect to EP_CLK. If EP_TRIGGER[x] is asserted for the rising edge of EP_CLK, then that trigger will be set. The next time the host checks trigger values, the triggers will be cleared.[/QUOTE]
Since most FPGA designs are synchronous, this generally means that the EP_TRIGGER signal will be asserted for a full clock cycle of EP_CLK.
It is not edge-sensitive, but you could probably craft some logic to convert an edge-sensitivity to a one-shot and that would perform the necessary translation.