I am trying to repeat the pipetest example using the HDL code provided in the Samples folder after FrontPanel installation.
I add all the necessary modules, .v files and .ngc files.
I receive an error in synthesis step saying:
[Synth 8-3966] non-net port ep_clk cannot be of mode input: `default_nettype is “none” [“X:/XEM7350/jj/jj.srcs/sources_1/imports/XEM7350-K160T/okLibrary.v”:146]
Pipetest should build without a problem in Vivado if it’s set up properly. Can you list the sources that you are including? Did you set the IS_GLOBAL_INCLUDE property on any of the sources?
You will need to set the TFIFO64x8a_64x8b.ngc source as a global include to properly synthesize the project, but we typically see this error when the top-level module is set as a global include as well. Please make sure that only the TFIFO source has the IS_GLOBAL_INCLUDE property set.
It looks like everything is there, but as I said, we typically see this error when a source (particularly a top-level source) is set as a global include when it shouldn’t be. Can you confirm that the only global include is the TFIFO source?