I am receiving a syntax error when synthesizing okCoreHarness.v
ERROR: [Synth 8-2715] syntax error near [/home/burkhart/projects/hv/code/verilog/arbitrary_clock_gen/okCoreHarness.v:10068]
XEM7001, Vivado v2015.2 (64-bit)
I am getting the same error. What was the resolution to your issue?
XEM7001, Vivado v2014.4 (64-bit) / Front Panel Version 4.5.6
This issue is typically caused by using an older version of Vivado, we recommend using the latest version possible. For the XEM7001 the minimum supported version is 2016.2.