Hi all. I have a question about encrypting the source files in verilog or VHDL:
1) Besides encryption which prevents the source code to be visible, is there any way to somehow limit the encrypted files to be used (in simulation) only on one machine? (For example, based on some compute's or work station's ID)
2) Is there any way to set an evaluation period for the encrypted files after which they cannot be used (in simulations)?
Thanks in advance.