I’m using the Verilog simulation models with FrontPanel-FC17-64-4.2.5 (the Windows version seemed to have 4.2.6 based on the installation filename). I’m trying to simulate the okBTPipeOut module. My issue is that the “ep_read” signal from this module is triggered on the negative edge of ti_clk. The FrontPanel manual seemed to show that it’s triggered on the positive edge.
I tried simulating the DES sample for the Windows installation (4.2.6). I had to make the following changes to make it run:
des.do: edit “PATH” so that it points to the actual simulation directory
destop.v: remove a “;” after “end”
des_tf: `include the correct path to “okHostCalls.v”
I got “Missing connection for port ‘hi_aa’.” warnings since it’s not in the design.
When I ran the simulation, I also saw that the “ep_read” signal is triggered on negative edge of ti_clk. Is this correct? The DES top module samples the “ep_read” signal on the positive edge of ti_clk even though it’s generated from the negative edge. Also, the pipe in modules seem to transfer signals onto the postive edge while the pipe out modules don’t.
So should I code my design expecting that the “ep_read” signal is generated on the negative edge and the “ep_datain” should be on the negative edge also?