In the RAMTester sampe for XEM6310, in MIG's memc3_infrastructure module, the global clock generation is done through the PLL_ADV primitive.
The input clock,
CLKIN1 is given the
sys_clk_ibufg signal, which is hooked up to the 100MHz oscillator on Y11 and AB11.
So this would mean the input clock frequency to PLL_ADV is 100MHz.
However, the same module's
CLKIN1_PERIOD is given
CLK_PERIOD_NS, which is
C_MEMCLK_PERIOD/1000.0=2.5. This means
CLKIN1_PERIOD_NS is 2.5ns, According to Xilinx UG382:
CLKIN1_PERIOD Specifies the input period in ns to the PLL CLKIN1 input
So this would mean the input clock is 400MHz, instead of 100MHz. As a result, the okPipeOut_fifo's wr_clk and okPipeIn_fifo's rd_clk would either be 12.5MHz or 50MHz...
Is this mismatch intentional? Or am I misunderstanding something?