RAMTester PLL_ADV parameters

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In the RAMTester sampe for XEM6310, in MIG’s memc3_infrastructure module, the global clock generation is done through the PLL_ADV primitive.

The input clock, CLKIN1 is given the sys_clk_ibufg signal, which is hooked up to the 100MHz oscillator on Y11 and AB11.
So this would mean the input clock frequency to PLL_ADV is 100MHz.

However, the same module’s CLKIN1_PERIOD is given CLK_PERIOD_NS, which is C_MEMCLK_PERIOD/1000.0=2.5. This means CLKIN1_PERIOD_NS is 2.5ns, According to Xilinx UG382:

CLKIN1_PERIOD Specifies the input period in ns to the PLL CLKIN1 input

So this would mean the input clock is 400MHz, instead of 100MHz. As a result, the okPipeOut_fifo’s wr_clk and okPipeIn_fifo’s rd_clk would either be 12.5MHz or 50MHz…

Is this mismatch intentional? Or am I misunderstanding something?

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I believe that the 2.5ns that you see for C_MEMCLK_PERIOD is just the default value given in that file. It appears as though the top level module (ramtest.v) overrides this value and sets it to 10,000(ps), which should result in 10ns period or 100MHz clock operation.

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@tom_mcleod
Ah that makes sense, that would give a 156.256MHz clock (it’s in the comments, but not sure how I missed that), which is half of the SDRAM’s 312.5MHz given in the datasheet. Thanks!