I get a problem when trying to simulate the ISE produced “post place and route” file up against the given test file “dut_tf”.
The tf works fine with the behavioural file. But when trying to simulate with the synthesized post place & route vhdl file, the response is poor. The signales like “hi_out”, “hi_inout” do not work properly, so the commands in the tf like wirein and trigin never gets updatet.
(using: questaSim6.3, ISE8.2 and dut_tf from frontpanel 3.0.9)
My assumption is that the test file simulate using the library “okFPsim”, while the synthesized file is being synthesized with the library “okLibrary”. And that this coupling does not work together.
Is my assumption correct, or does anyone have any suggestions on what to do in this situation?