I'd like to do a timing simulation (post-place & route) of my design (which involves I/O via the Frontpanel host interface) in Xilinx ISim 13.4. I wrote a Verilog testbench that uses calls to the procedures in okHostCalls.v to simulate I/O via the ok host interface (as described in the Frontpanel manual), and the behavioral simulation using this testbench works fine.
Next, I generated a post-place & route simulation model in ISE project manager and tried to run the post-place & route simulation using the same test bench as above. However, during the syntax check step I get the following error:
ERROR:HDLCompiler:281 - "testbench.v" Line 167: Cannot open include file "okHostCalls.v".
-- although okHostCalls.v is on the library path and gets included successfully in the behavioral simulation. The simulation starts nevertheless, but the Frontpanel stimulus specified in the testbench doesn't happen. Is this the expected behavior, or am I making a mistake? Is it in principle possible to do a post-place & route simulation using the Frontpanel simulation libraries?
Note that I don't need/want to simulate the detailed timing of the Frontpanel IP cores, I just need some stimulus to download some data and trigger events.
Any help apreciated,