Ok so I predominantly come from an extensive VHDL background, yet im trying to understand the syntax in the OKHost verilog samples (shown below)
-- begin
[COLOR="#FF0000"]wire [65*3-1:0] okEHx; // (195-1) : 0 [/COLOR]
okHost okHI(
.okUH(okUH),
.okHU(okHU),
.okUHU(okUHU),
.okAA(okAA),
.okClk(),
.okHE(okHE),
.okEH(okEH)
);
[COLOR="#FF0000"]okWireOR # (.N(3)) wireOR (okEH, okEHx); // 3[/COLOR]
okWireIn wi00(.okHE(okHE), .ep_addr(8'h00), .ep_dataout(ep00wire));
okWireOut wo20(.okHE(okHE), .okEH([COLOR="#FF0000"]okEHx 0*65 +: 65 ][/COLOR]), .ep_addr(8'h20), .ep_datain(ep20wire)); [COLOR="#FF0000"] /// what is 0*65 +: 65 and how does it translate[/COLOR]
okWireOut wo22(.okHE(okHE), .okEH([COLOR="#FF0000"]okEHx 1*65 +: 65 ][/COLOR]), .ep_addr(8'h22), .ep_datain(ep22wire));
okTriggerIn ti40(.okHE(okHE), .ep_addr(8'h40), .ep_clk(sys_clk), .ep_trigger(ep40wire));
okTriggerOut to60(.okHE(okHE), .okEH(okEHx 2*65 +: 65 ]), .ep_addr(8'h60), .ep_clk(sys_clk), .ep_trigger(ep60trig));
[COLOR="#FF0000"]// what /how does okEH(okEHx 2*65 +: 65 ]) work?? [/COLOR]
-- end
I tried making the code a bit more understandable, but my implementation for some reason seems to have an issue - when using frontpanel components - it looks like the signals are getting crossed somehow :
it synthesizes, and all but when tying a counter to endpoint 0x22 i sometimes see the data on endpoint 0x20 - and so my front panel xml gui gets all weird. and im not a fan of super convoluted verilog statements - and dont understand how the default code (above) works with its " N*65 +: 65 " code
this code below makes more sense to me but doesnt seem to work right -- [COLOR="#0000CD"]and im trying to figure out WHY[/COLOR] :
-- begin
parameter OK_endpoints = 3;
[COLOR="#FF0000"]wire (65*OK_endpoints)-1:0] okEHx; // (3*65)-1 : 0 => (195 -1) : 0[/COLOR]
okHost okHI(
.okUH(okUH),
.okHU(okHU),
.okUHU(okUHU),
.okAA(okAA),
.okClk(),
.okHE(okHE),
.okEH(okEH)
);
okWireOR # (.N(OK_endpoints)) wireOR (okEH, okEHx); // 3
okWireIn wi00(.okHE(okHE), .ep_addr(8'h00), .ep_dataout(ep00wire));
okWireOut wo20(.okHE(okHE), .okEH([COLOR="#FF0000"]okEHx(1*65)-1:0*65][/COLOR]), .ep_addr(8'h20), .ep_datain(ep20wire)); [COLOR="#FF0000"]// (65-1) :0[/COLOR]
okWireOut wo22(.okHE(okHE), .okEH(okEHx(2*65)-1:1*65]), .ep_addr(8'h22), .ep_datain(ep22wire)); [COLOR="#FF0000"]// (130-1):65[/COLOR]
okTriggerIn ti40(.okHE(okHE), .ep_addr(8'h40), .ep_clk(sys_clk), .ep_trigger(ep40wire));
okTriggerOut to60(.okHE(okHE), .okEH(okEHx(3*65)-1:2*65]), .ep_addr(8'h60), .ep_clk(sys_clk), .ep_trigger(ep60trig)); [COLOR="#FF0000"] // (195:1) : 130[/COLOR]
-- end
my main interest is why doesn't my code above work, as it looks very similar to the default VHDL code provided by O.K., which also makes sense :
but im currently doing a verilog design
-- begin
[COLOR="#FF0000"]signal okEHx : STD_LOGIC_VECTOR(65*3-1 downto 0);[/COLOR]
-- Instantiate the okHost and connect endpoints
okHI : okHost port map (
okUH=>okUH,
okHU=>okHU,
okUHU=>okUHU,
okAA=>okAA,
okClk=>open,
okHE=>okHE,
okEH=>okEH
);
okWO : okWireOR generic map (N=>3) port map (okEH=>okEH, okEHx=>okEHx);
ep00 : okWireIn port map (okHE=>okHE, ep_addr=>x"00", ep_dataout=>ep00wire);
ep20 : okWireOut port map (okHE=>okHE, okEH=>[COLOR="#FF0000"]okEHx( 1*65-1 downto 0*65 )[/COLOR], ep_addr=>x"20", ep_datain=>ep20wire); [COLOR="#FF0000"] -- ((65-1) downto 0); -- makes sense[/COLOR]
ep22 : okWireOut port map (okHE=>okHE, okEH=>[COLOR="#FF0000"]okEHx( 2*65-1 downto 1*65 )[/COLOR], ep_addr=>x"22", ep_datain=>ep22wire); [COLOR="#FF0000"] -- ((130-1) downto 65);[/COLOR]
ep40 : okTriggerIn port map (okHE=>okHE, ep_addr=>x"40", ep_clk=>sys_clk, ep_trigger=>ep40wire);
ep60 : okTriggerOut port map (okHE=>okHE, okEH=>okEHx( 3*65-1 downto 2*65 ), ep_addr=>x"60", ep_clk=>sys_clk, ep_trigger=>ep60trig);
-- end