Couldn’t reply to the software downloads thread - no permissions–, but anyway, real quick because I’m off for the weekend… Looks like a good start. Proposed looks good at first glance. I noticed that you do not have any of the ports worked out yet. I found for myself that the inout is a problem internally, I think this is because ISE can handle internal TRI-STATE but not XPS… I think it would help to get rid of the inout and have an in bus and an out bus like everything else in the microblaze. In fact it might help to recompile the old design to get rid of the interconnect TRI-STATE liability in general…
The next version of FrontPanel (see announcements for beta package) does away with the inout ti_data bus and has an input only and output only bus.
This, combined with block throttled pipes should make for more interesting combinations into MicroBlaze. For instance, we should be able to break things out into multiple peripherals with Block Throttled pipes able to stream data into a FSL peripheral while Wires and Triggers remain in an OPB peripheral.
BTW, what did you mean by “not have any of the ports worked out yet”? I have a good assortment of wires, triggers, and a pipe in and pipe out implemented.
I build some OPB master peripherals to do the DMA transfers. DMA is the real solution for PIPE transfers bottlenecks. The problem is that the Microblaze v4 doesn’t like more than one master on a bus and OPB seize to function. I hope they solved this issue with MB v5. To use FSL to get the data to the processor and then to RAM may be a workaround, but I doubt of the performance.
Regarding tristates: ti_data (INOUT) should be transferred into ti_data_I (IN), ti_data_O (OUT) and ti_data_T (OUT). All the pins are mapped into TBUF, where the ti_data_T is a toggle pin which controls the output enable (active low). You define tristate in MPD as
PORT ti_data = “”, DIR = INOUT, ENABLE=SINGLE, THREE_STATE=TRUE.
“ENABLE=SINGLE” stands for single pin ti_data_T (not a vector).