Modelsim (Mentor) is really making your life miserable. I just downloaded the only copy of the Modelsim tool from the Xilinx site. It is 6.4b.
I added your 6.3c libraries into the Workspace, but it fails to simulate with those models showing the error below.
Would it not be easier for you to create encrypted Verilog models that are simulator agnostic?
** Fatal: (vsim-3381) Obsolete library format for design unit. (See design unit listed above.)
Time: 0 ps Iteration: 0 Instance: /test_ddr2_tf/u_ramtest File: ../ramtest.v
FATAL ERROR while loading design
Error loading design
No Design Loaded!