FP Core needs to be modified to avoid chip Errata on Spartan 6

The FP Core generates this warning message:

[INDENT]WARNING:PhysDesignRules:2212 - Async clocking for BRAM (comp
host/core0/core0/lbi_0/ser_0/tdpram_0/BU2/U0/blk_mem_generator/valid.cstr/ram
loop[1].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram) port(s) with READ_FIRST mode
has certain restrictions. Make sure that there is no address collision. A
read/write on one port and a write operation from the other port at the same
address is not allowed. RAMB16BWER, when both ports are 18 bits wide or
smaller, A13-6 including A4 cannot be same. When any one port is 36 bits
wide, A13-7 including A5 cannot be the same. Violating this restriction may
result in the incorrect operation of the BRAM.
[/INDENT]
The work around for this BRAM issue is to change the mode to WRITE_FIRST. See the Spartan 6 Errata. (Xilinx en148.pdf)

Please update the core to fix this problem.Thanks…