Factors req to choose VHDL or Verilog

i am fairly good VHDL designer, and have a superficial overview of verilog. i have read many articles through google search engine about comparison between VHDL and verilog. but most of them i felt were biased. i couldn’t get any link which illustrates the advantages and disadvantages of VHDL over Verilog. please help me find the present status of these two HDLs. also, i heard that VITAL is used as a cross-link to verilog primitives to provide VHDL the edge for gate level modeling, is that true?. in using mixed HDL design of both VHDL and verilog how can we get maximum benefit, i.e, what are the areas we should prefer using VHDL or Verilog and vice-versa.
where can i get illustration about the factors required to one of them

For what it’s worth, here is a very basic, unofficial, from-the-hip response:

For most synthesis-oriented tasks, VHDL and Verilog are very similar. In fact, HDL code written with synthesis constructs only can almost always be translated on a line-by-line basis.

This is not true for deeper behavioral models that use more intricate details of the languages, but if you’re targetting an FPGA, you could choose either.

VHDL is more verbose.

Newcomers typically find Verilog more familiar. VHDL is an “easy-learn” after you’ve picked up Verilog.

If you’re starting from scratch (no HDL experience) and are doing a smallish synthesis design, I’d go with Verilog.

If you’re doing something bigger that may require more interfacing to simulators, something akin to object-oriented design, or needs stricter type control, VHDL may be better.

If you have prior experience, pick what you know.

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