For what it's worth, here is a very basic, unofficial, from-the-hip response:
For most synthesis-oriented tasks, VHDL and Verilog are very similar. In fact, HDL code written with synthesis constructs only can almost always be translated on a line-by-line basis.
This is not true for deeper behavioral models that use more intricate details of the languages, but if you're targetting an FPGA, you could choose either.
VHDL is more verbose.
Newcomers typically find Verilog more familiar. VHDL is an "easy-learn" after you've picked up Verilog.
If you're starting from scratch (no HDL experience) and are doing a smallish synthesis design, I'd go with Verilog.
If you're doing something bigger that may require more interfacing to simulators, something akin to object-oriented design, or needs stricter type control, VHDL may be better.
If you have prior experience, pick what you know.